With ever increasing demands to reduce both the size of devices and their power consumption, it is becoming increasingly challenging to design robust semiconductor memories such as SRAM. Each storage cell in an SRAM comprises a feedback loop for holding a data value. In order to write to the feedback loop and store a new value, the input data value must have a high enough voltage level to be able to switch the state stored by the feedback loop if required, while reading from the feedback loop should be performed without disturbing the values stored in any of the feedback loops.
When accessing a storage cell in such memories access devices are turned on in a row by charging a word line, the data lines or bit lines are then connected to the cells. These bit lines have been precharged during a precharge phase and now that the access devices are turned on, either the value stored in the cell is transferred to the bit lines, or a value to be written to the cell is transferred to the bit lines and this is then transferred to the cell via the access transistors. In a write the data value is placed on the bit lines of the cell to be written to by allowing one of the bit lines to decay to zero while driving the other, the access transistors are turned on and the feedback loop is connected to the bit lines and the data value on the bit lines is stored in the feedback loop. When reading from a cell both bit lines are pre-charged and the side of the cell storing a 0 will pull down the bit line when it is connected to it and this change in voltage level can be detected to determine on which side of the feedback loop the 0 is stored. However, the difference in voltage levels between the precharged bit line and the 0 node of the feedback loop may result in the node storing a 0 being pulled up towards 1 resulting in instability in the bit cell and the bit cell flipping value. This is called read disturb and can happen to a cell during a read to a cell or during a write to another cell on the same word line. This is a consequence of the word line turning on all access devices in a row even though only a subset (generally one) of the cells in the row is to be accessed.
In devices where the capacitance of the power node of the wordline driver is high it is difficult to control the voltage transferred to the word line when it is connected to the driver. This can result in wordline voltage rising quickly and access devices being turned on quickly. This results in the pre-charged bit lines being connected to the half-selected storage cells before their voltage levels have decayed significantly making a disturb of the cell more likely.
Memories with a large number of rows and with relatively few columns are particularly, susceptible to this problem as they have increased capacitance on the power node of the wordline driver and the wordline is smaller and therefore voltages can rise more quickly. Furthermore as memories reduce in size process variations increase and therefore so do access disturbs.
It would be desirable to be able to reduce access disturbs of a semiconductor memory.